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Mrinal Iyer

Mrinal Iyer

Performance Lead

Mrinal is a versatile engineer and leader, with experience working across all parts of the semiconductor industry (architecture, kernels & compilers, applications, fab etc). Prior to joining Modular, he spent 6 years working for Deep Learning ASIC startups (Graphcore and Nervana) and brings in a wealth of knowledge on full stack performance of AI applications, starting from the models to frameworks, compilers, runtimes and assembly. At Graphcore, he led the effort to create highly performant and scale-out training implementations of BERT & Resnet for MLPerf. He enjoys spending his free time with family, trail running and cooking.

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